1. Field of the Invention
The invention relates to a method for error detection/correction of a multilevel cell memory which can store a plurality of bits of information in each single memory cell.
2. Description of the Related Art
In general, semiconductor memories store a single bit of information in each single memory cell thereof. In writing and reading data, such semiconductor memories as a flash memory generate simple error correcting codes (ECCs) by access to their memory cells, and compare these ECCs to perform the detection/correction of single-bit errors.
FIGS. 1 and 2 show a method for detecting/correcting a single-bit error in a flash memory. For simplicity, the following description deals with the case of accessing (writing/reading) memory cells in steps of eight bits. In actual flash memories, read operations and write operations are performed, for example, in steps of 4096 bits. In this embodiment, odd parity codes are used as ECCs.
In this example, data bits grouped by the value in one bit of their binary bit addresses BA, there being a group identified for each address bit for each address bit value thereof, are used to generate parity codes. Binary bit addresses BA are binary representations of physical bit addresses PA which designate individual memory cells. Since eight memory cells are in question, a binary bit address BA is composed of three bits. Hereinafter, description will be given of the case where write data WD of “10010110” in binary is written to the memory cells, and read data RD of “10010010” in binary is read from the memory cells. That is, a data error occurs in the memory cell having a physical bit address PA of “2”.
As shown in FIG. 2, the number of bits of parity codes P0–P5 is set at six bits, or twice the number of bits of a binary bit address BA. The parity code P0 is calculated from the data corresponding to four binary bit addresses BA that have “0” in their least significant digits. That is, the parity code P0 is generated from the data to be written/read under four physical bit addresses “0”, “2”, “4”, and “6” corresponding to binary bit addresses “000”, “010”, “100”, and “110”.
The parity code P1 is calculated from the data corresponding to four binary bit addresses BA that have “1” in their least significant digits. That is, the parity code P1 is generated from the data to be written/read under four physical bit addresses “1”, “3”, “5”, and “7” corresponding to binary bit addresses “001”, “011”, “101”, and “111”.
Similarly, the parity codes P2 and P4 are calculated from the data corresponding to four binary bit addresses BA that have “0” in their second digits and third digits (most significant digits), respectively. The parity codes P3 and P5 are the parities of data corresponding to four binary bit addresses BA that have “1” in their second digits and third digits (most significant digits), respectively.
In this way, each bit of writing parity code WP and each bit of reading parity code RP are obtained from predetermined four bits of the write data WD (“10010110”) and predetermined four bits of the read data RD (“10010010”) shown in FIG. 1.
The parity codes P0–P5 are generated for situations where binary bit addresses BA have “0” or “1” in respective digits as described above. Therefore, when a single-bit error occurs, comparisons between the individual bits of the parity codes WP and RP indicate that either of the parity codes P0 and P1, either of the parity codes P2 and P3, and either of the parity codes P4 and P5 are inverted. Specifically, as shown in FIG. 2, the underlined error-occurring binary bit address BA (“010”) is included in either of the parity codes P0 and P1, in either of the parity codes P2 and P3, and in either of the parity codes P4 and P5. Therefore, if the exclusive ORs of the parities P0–P5 and the parities WP and RP (WP XOR RP) indicate differences between the parity codes P0 and P1, between the parity codes P2 and P3, and between the parity codes P4 and P5, then a single-bit error is detected. Here, the value of the error-occurring binary bit address BA is given by arranging the parity codes P5, P3, and P1 (“010” in this example). Then, the data read from this address is inverted for error correction.
Recently, the data amount to be handled in portable equipment with flash memory mounted, and the like, has been on the increase, requiring flash memories of yet larger capacities. For this reason, there have been developed four-level cell flash memories which can store two bits of information in each single memory cell.
FIG. 3 shows the relationship between logical values of data and threshold voltage VTH in a flash memory that can store two bits of information in each single memory cell.
For example, when a memory cell has a threshold voltage VTH lower than the reference voltage V1, the data retained in the memory cell is “00”. When the threshold voltage VTH of a memory cell falls within the range of the reference voltages V1 and V2 the data retained in the memory cell is “01”. When the threshold voltage VTH of a memory cell falls within the range of the reference voltages V2 and V3 the data retained in the memory cell is “10”. When the threshold voltage VTH of a memory cell exceeds the reference voltage V3 the data retained in the memory cell is “11”. In the flash memory of this type, memory cell currents which vary with the threshold voltage VTH are compared with a plurality of reference currents to read data retained in the memory cells.
Four-level cell flash memories having memory cells capable of storing two bits of information can lose control of threshold voltages in write operations if defects occur among the memory cells. This means higher chances of a two-bit error in the same memory cell. Accordingly, multilevel cell flash memories of this type cannot fully relieve defects by simply performing the detection/correction of single-bit errors.
The four-level cell flash memory described above can adopt a conventional technique for detecting/correcting two-bit errors to improve the error-detection/correction efficiencies. Nevertheless, conventional circuits for detecting/correcting two-bit errors are far more complicated than those for detecting/correcting single-bit errors. Therefore, the implementation of a two-bit error detecting/correcting circuit on a flash memory has caused problems of greater chip sizes and increased fabrication costs. Moreover, a two-bit error detecting/correcting circuits have longer error-detecting/correcting times as compared with single-bit error detecting/correcting circuits. This may preclude error correction within read cycle time when four-level cell flash memories capable of high-speed reading are developed in the future.
Furthermore, semiconductor memories that store eight levels and sixteen levels in each single memory cell are apt to three-bit errors and four-bit errors, respectively. Nevertheless, there has been proposed no error-detection/correction technique that is tailored to a multi-bit defect occurring in a single multilevel memory cell.